Research Review · 2026-10-12 · Semiconductors & Advanced Computing

When Probabilistic Models Meet Probabilistic Hardware

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Research Review

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Research Synthesis: Analysis of existing evidence and literature. No new Ethen measurements are implied.Literature-based analysis; no original hardware experiments; not peer reviewed

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Semiconductors & Advanced Computing

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October 12, 2026

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Shadab Chow, Ethen Research Lab, Upcube

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1.0

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A critical review of measured, simulated and claimed advantages of physical probabilistic computing, with a reporting checklist for quality-matched, boundary-closed comparison

Ethen Research Lab · Research Review · Version 1.0 · Not Peer Reviewed

Literature-Based Analysis · No Original Hardware Experiments

Paper ID: P2-01 · Article type: Research Review / Working Paper · Literature cutoff: 11 October 2026 · Version: 1.0 · Published: 12 October 2026

Author: Shadab Chow

Affiliation: Ethen Research Lab, Upcube. Correspondence: shadabchow@gmail.com · Corrections: shadabchow@gmail.com

Publication status. This research review is self-published by Ethen Research Lab. It has not been peer-reviewed and has not been submitted to a journal. It is a literature-based analysis. The authors and their organisation have not fabricated hardware, run chip experiments, or measured the performance of any device discussed here. Every numerical result is a third-party result or our arithmetic on third-party figures, labelled by evidence class. The critical review passes used in preparing this version were AI-assisted editorial checks. They are not independent human peer review.

Abstract

Probabilistic computers built from intrinsically stochastic elements (p-bits, stochastic and voltage-controlled magnetic tunnel junctions, CMOS noise sources, ferroelectric random-telegraph devices and thermodynamic analog circuits) are proposed as energy-efficient substrates for sampling from energy-based models, for combinatorial optimisation and, most recently, for diffusion-like generative modelling. Published headline advantages over conventional digital hardware range from one to more than six orders of magnitude. We ask whether these advantages hold at matched task quality and at a stated, closed system boundary. We review primary sources available to 11 October 2026 and classify each load-bearing claim as measured, simulated, analytically modelled or vendor-claimed, recording its workload, baseline, quality metric and system boundary. Four findings follow.

1. The most prominent 2026 result, a roughly 10,000-fold energy advantage per generated image for a denoising thermodynamic architecture, is an inference-only projection from a simulator and a physical energy model. Only the architecture's random-number circuit was measured, and no full device exists.
2. Where measured system data exist, control and interface electronics dominate. A 1,143-p-bit 130-nm ASIC and its control board drew 395 mW while solving, against 9 mW for its entropy-source board. Its experimental device-level entropy cost of 34.4 pJ per random bit compares with a 0.43 pJ projection. In a CMOS p-bit demonstration, the FPGA post-implementation power estimate was about 10⁴ times the derived power of one p-bit core. In a vendor's own energy model, the sign of a stated 139-fold advantage depends on where the dense readout runs and on the assumed GPU utilisation. The resulting interval of roughly 14–139-fold better to 3–33-fold worse is modelled, not measured.
3. No reviewed fabricated sampler reports effective sample size or energy per effective independent sample. This absence is bounded by the search we could perform.
4. The one matched trial of physical versus good pseudo-random entropy that we found reported parity on a sampling-accuracy benchmark.

These findings do not show that probabilistic hardware cannot win. They show that the evidence needed to decide has not yet been published. We also present a reporting checklist and map each of its elements to existing statistical and benchmarking methods. Its components are not new. It is a synthesis that asks for these elements to be reported together when probabilistic-hardware efficiency is claimed.

Keywords: probabilistic computing; p-bits; Ising machines; energy-based models; thermodynamic computing; effective sample size; autocorrelation; burn-in; system boundary; benchmarking methodology; magnetic tunnel junctions; denoising thermodynamic models

1. Introduction

1.1 Motivation

Sampling is a computational primitive with a long history. Simulated annealing [1], Gibbs sampling [2] and the Boltzmann machine [3] all rest on drawing configurations from a distribution of the form $p(\mathbf{x}) \propto \exp[-\beta E(\mathbf{x})]$. On conventional digital hardware, each stochastic update costs a pseudo-random number, a weighted sum and a comparison, which amounts to tens to hundreds of deterministic logic operations spent on emulating randomness. A family of hardware proposals inverts this. It uses physical noise as the source of randomness and lets the hardware relax stochastically toward the target distribution. Instances include probabilistic bits (p-bits) [7, 38], stochastic and voltage-controlled magnetic tunnel junctions (sMTJs, V-MTJs) [8, 21, 23], CMOS shot- or thermal-noise generators [15, 22], ferroelectric random-telegraph sources [25], charge-trap transistors [26] and coupled analog oscillator circuits [31, 32]. Thermodynamic computing proposals extend the idea to continuous Langevin dynamics [33, 41].

Since 2024 the field has moved from demonstrations on fixed problems toward generative AI. A denoising thermodynamic computer architecture (DTCA), posted as a preprint in October 2025 and published in July 2026, estimates that a probabilistic chip could match a GPU on a simple image-generation benchmark while using roughly 10,000 times less energy per generated sample [15]. A commercial developer has published sparse transformer-like models for a forthcoming sampling chip and states efficiency ratios of 14–139 times relative to an H100 GPU [16]. In parallel, several fabricated or board-level p-bit systems with real measurements have appeared [18–22, 24–26]. The contrast between large modelled claims and modest measured systems is the subject of this review.

1.2 The comparison problem

An efficiency claim for a probabilistic computer is a ratio, and both its numerator and its denominator are easy to misstate. Four problems recur.

1. Evidence class. A ratio may compare a measured device with a measured GPU, a simulated device with a modelled GPU, or a projected future device with a nominal datasheet figure. These are different scientific objects.
2. System boundary. Energy may be counted for the entropy source alone, the p-bit cell, the array, the board including converters and FPGA helpers, the node including the host, or the facility including cooling (Figure 2). Ratios computed at different boundaries cannot be compared.
3. Sample quality. Markov-chain samples are autocorrelated. A flip, a sweep and an effective independent sample are different denominators, and the ratio between them can be orders of magnitude [4–6]. Effective-sample counts also measure estimation precision, not bias. A sampler can be precise and wrong [5, 46].
4. Task quality. Two systems match on a task only when they reach the same quality threshold: the same Fréchet Inception Distance (FID) [13], the same residual energy, the same success probability or the same optimality gap.

1.3 Research questions

• RQ1. Which reported advantages of physical probabilistic hardware over conventional digital hardware are physically measured, and which are simulated, analytically modelled or vendor-claimed?
• RQ2. At which system boundary is each advantage stated, and how does the advantage change when the boundary is closed?
• RQ3. Do any hardware studies report sampling efficiency in units of effective independent samples? If not, how much uncertainty does that leave, and under what statistical conditions would such a figure be valid?
• RQ4. What do the strongest positive and negative results say about the conditions under which probabilistic hardware could deliver a real, quality-matched advantage?
• RQ5. Which reporting elements would make future claims comparable, and how many of them already exist in established methodology?

1.4 Contribution and its limits

This article is a review and synthesis. It makes three contributions.

1. An evidence-class and boundary audit of the principal 2024–2026 claims, verified against primary sources where accessible, with every unread source listed.
2. A bounding analysis connecting device-level and system-level efficiency. It applies Amdahl's law [40] to energy and states explicitly that the bound covers only component substitution (§3.5).
3. A reporting checklist (§8) whose elements map one-to-one onto established methods. These are MCMC diagnostics and their known failure modes [4–6, 43–46, 52], time-to-solution conventions [10, 47], benchmarking-quality and parameter-tuning guidelines [48, 49], and whole-system power measurement [37].

A prior-art mapping (Table 5) shows that no single element of the checklist is new. We claim no invention, validated novelty or community consensus for it. We report only that we did not find, in the literature we could search, a guideline requiring these elements together for probabilistic-hardware efficiency claims, and that statement is bounded by our search. The authors have built no hardware and measured nothing.

2. Review methodology

2.1 Design

The review is structured and critical. It is not a formal PRISMA systematic review, because the bibliographic databases a systematic review requires were not accessible (§2.5). Its scope is physical probabilistic computing applied to sampling, optimisation and generative modelling, with emphasis on 2024–2026 results and on claims that compare against CPUs, GPUs or other conventional hardware.

2.2 Sources

Evidence came from two streams.

1. Internal literature notes. These are research notes compiled by Ethen Research Lab during 2026: source registries, contradiction registers, negative-search logs and dossiers on probabilistic hardware. We used them only to find leads. No number in this article rests on internal notes alone unless it is explicitly labelled that way. Where our checks of primary sources disagreed with the notes, the primary source governs. The corrections are recorded in the companion audit files, not in this article.
2. Primary literature. For every source carrying a load-bearing number, we retrieved the publisher page, preprint-server record or first-party page, most recently on 11 October 2026. Bibliographic metadata were checked against Crossref records where the Crossref service was reachable. §2.6 states the depth at which each source was read.

2.3 Search record

The search used general web search, preprint servers, publisher sites and the Crossref metadata service. It did not use subscription bibliographic databases. Table 0 lists the searches behind each absence statement in this article.

Table 0. Search record supporting the absence statements in this article.

The internal search logs record stopping rules, such as halting a query family after three variants when results became pre-2024 or off-topic. We report such absences as not found in the reviewed literature, never as proof that a result does not exist.

2.4 Classification scheme

Each claim was assigned one evidence class:

• M-sys: measured on fabricated hardware at a stated system boundary;
• M-dev: measured at device or cell level only;
• SIM: numerical simulation, including emulation of the proposed hardware on a GPU or CPU;
• MOD: analytical or physical energy model, including PDK-based circuit estimates and projections;
• VEN: vendor or first-party claim without independent verification;
• SEC: secondary report only.

For each claim we also recorded the workload, quality metric, comparator, how the comparator's energy was obtained, and the boundary level B0–B5 shown in Figure 2. Vendor-authored peer-reviewed papers (for example [15]) are classified by their content (SIM, MOD, M-dev) and additionally flagged as vendor-authored. Numbers we computed from published figures are labelled "our arithmetic".

2.5 Verification depth and database access

Each claim was verified against the deepest source we could access. In order of decreasing depth:

• full primary text;
• a primary abstract, landing page or figure captions;
• Crossref or arXiv metadata only;
• standard bibliographic knowledge without retrieval (marked [K] in the references).

The claim-by-claim record is maintained with this version and is available from the corresponding author on request. Scopus, Web of Science, IEEE Xplore and the ACM Digital Library were not available, and earlier IEEE Xplore requests returned access errors. The review is therefore not systematic. Conference proceedings (IEDM, ISSCC, VLSI) were covered only through openly available versions.

2.6 Sources not fully read

The following were not read in full and are cited only at the stated depth:

• Duffee et al. [21]: preprint read in full; Version-of-Record abstract and Extended Data captions read; Version-of-Record main text and Supplementary Information not read (paywalled).
• Li et al. [20]: Version-of-Record landing page and arXiv/Research Square abstracts read; full text and Supplementary Information not read.
• Supplementary materials for [18], [19], [22] and [25]: not read.
• Abstract level only: Kubo and Goto [34], Bernal Neira et al. [48], Acuaviva et al. [49], Margossian and Gelman [45], Antunes and Hill [50].
• Not re-retrieved because the metadata service rate-limited our request: Landauer [12]. It is cited from standard bibliographic knowledge.

3. Scientific and mathematical foundations

3.1 p-bits and Gibbs sampling

Consider binary spins $m_i \in \{-1, +1\}$ with energy

The Gibbs conditional for spin $i$ is

where $\sigma$ is the logistic function. The p-bit update rule [7] implements Eq. (2) as

using the identity $\tfrac{1}{2}[1+\tanh(\beta I)] = \sigma(2\beta I)$. A physical p-bit replaces the explicit random number $r$ with device noise. Its tunable sigmoidal response approximates $\tanh(\beta I_i)$. The weighted sum $I_i$ is still computed by some other circuit: an FPGA, a digital multiply–accumulate unit, an analog crossbar, or hard-wired local couplings. This separation is the root of the boundary problem analysed in §5. Correct Gibbs sampling also requires that coupled spins are not updated simultaneously. In practice this means graph colouring, chromatic scheduling or asynchronous operation [9, 18]. Onizawa and Hanyu [30] analyse how excessive synchronous updates cause oscillation and how asynchronous updates are slowed by hardware delay.

3.2 Autocorrelation and effective sample size

Let $f_t = f(\mathbf{m}_t)$ be a scalar statistic recorded after each sweep of a chain, with normalised autocorrelation $\rho_k$ at lag $k$. For a chain at stationarity, the integrated autocorrelation time and the effective sample size of $N$ post-burn-in draws are [4, 6]

We use the convention $\tau_{\mathrm{int}} = 1 + 2\sum_k \rho_k$ (as in Geyer [4] and Vehtari et al. [5]). Some statistical-physics texts define $\tau_{\mathrm{int}}$ as half this value [6], so published numbers must be compared within one convention. Eq. (4) defines a population quantity. Using it on hardware data requires conditions that are often assumed without being stated, and we list them below. They are taken from the cited statistical literature and have not been reviewed by an independent statistician (§9).

• C1. Stationarity. Eq. (4) applies only to draws taken after the chain has reached its stationary distribution. Burn-in (warm-up) must be identified and excluded. Margossian and Gelman [45] distinguish nonstationary variance, which reflects initialisation and is removed by adequate warm-up, from persistent variance, which remains after convergence and is what ESS addresses.
• C2. Estimator assumptions. The infinite sum must be truncated. Geyer's initial positive and monotone sequence estimators [4] are asymptotically conservative for reversible Markov chains at stationarity. Systematic-scan and chromatic Gibbs samplers are not reversible in general. Physical samplers with hidden device state, 1/f noise or drift may not be Markov in the observed spins at all. For such series, standard ESS estimators are heuristics whose guarantees do not formally apply [5, 4].
• C3. Downward bias under positive correlation. Common lag-window (spectral) and batch-means estimators of the asymptotic variance show significant negative bias when the process is positively correlated [44]. Underestimated variance means overestimated ESS. A strongly correlated physical sampler is exactly the case in which naive ESS estimates are most optimistic.
• C4. Multiple chains. Multi-chain diagnostics should use rank-normalised split-$\hat{R}$ with bulk and tail ESS [5]. Vehtari et al. recommend $\hat{R} < 1.01$ and bulk/tail ESS of at least about 400 before quantities are trusted. Many short chains can mislead because each may retain initialisation bias [5, 45]. Efficient multi-chain initial-sequence estimators exist [52].
• C5. ESS measures precision, not correctness. ESS and $\hat{R}$ assess how precisely an expectation is estimated. They do not show that the samples represent the target distribution [5]. A biased sampler can have a large ESS.

ESS also depends on the statistic: a sampler can mix quickly for magnetisation and slowly for a tail probability. For multimodal energy landscapes, $\tau_{\mathrm{int}}$ typically grows roughly exponentially with $\beta\,\Delta E_{\mathrm{barrier}}$. This is an Arrhenius-type heuristic for barrier crossing, not an exact law. This is the mechanism behind the mixing–expressivity trade-off that the DTCA authors identify [15].

Condition C5 is especially important for physical hardware. For a stationary chain that satisfies a Markov-chain central limit theorem, the mean-squared error of a Monte Carlo estimate $\hat{\mu}_f$ from $N$ post-burn-in draws decomposes, for large $N$, as

where $\tilde{p}$ is the distribution the hardware actually samples. Physical samplers have several sources of $\tilde{p} \neq p$:

• an imperfect sigmoid, or an output probability that drifts with voltage and temperature [22];
• device-to-device spread [22];
• biased raw entropy [21];
• simultaneous updates of coupled spins [27, 30];
• an effective temperature that differs from the nominal one, which non-MCMC samplers must estimate explicitly [34].

ESS controls only the second term of Eq. (4a). Bias must be checked separately, for example by exact enumeration on small instances (KL divergence to the Boltzmann distribution, as in [23]) or by simulation-based calibration. Talts et al. show that dependent posterior samples make simulation-based-calibration rank histograms deviate from uniformity, producing spikes at the extremes, and that thinning to roughly the effective sample size removes the artefact [46].

3.3 From raw throughput to effective throughput

A machine with $N_p$ p-bits, each updated at mean rate $f_{\mathrm{u}}$, produces $N_p f_{\mathrm{u}}$ flips per second (FPS). One sweep corresponds to $N_p$ attempted updates. For asynchronous hardware, a sweep is defined in the same way, by update count rather than by a clock. For a single chain, the effective sampling rate for statistic $f$ is

Now suppose $C$ independent chains run concurrently inside boundary $B$ at total average power $P^{B}$. Each chain spends time $t_{\mathrm{burn}}$ in warm-up and $t_{\mathrm{samp}}$ in sampling. Assume conditions C1–C4 hold and the chains mix equally. The pooled ESS is then $C f_{\mathrm{u}} t_{\mathrm{samp}}/\tau_{\mathrm{int}}^{(\mathrm{sweep})}$, and the energy per effective sample is

Warm-up is paid once per chain. Running many short chains (large $C$, small $t_{\mathrm{samp}}$) inflates the warm-up term, which is the hardware counterpart of the many-short-chains warning in [5, 45]. Eq. (6) addresses precision only. A quality-matched claim must also bound the bias term in Eq. (4a). Eq. (6) also shows that a device $k$ times more energy-efficient per flip but with a $k$ times longer autocorrelation time gives no net benefit. Berns et al. [29] make the same dependence explicit: stochastic Ising-machine sampling of quantum Heisenberg models showed much longer autocorrelation times than the baseline, and the projected 100–10,000-fold speed-up rests on parallelism compensating for that correlation.

3.4 Quality-matched task metrics

For optimisation, the standard quality-normalised time metric is the time to reach a target (for example, the optimum or 95% of it) with probability $p$ [10, 47]:

where $p_s$ is the per-run success probability. Böhm et al. [47] use $p = 0.99$. Eq. (7) diverges as $p_s \to 0$, so TTS is undefined for instances never solved. When $p_s \ge p$ the formula gives a value below $t_{\mathrm{run}}$, and implementations usually cap TTS at one run. TTS should be reported with confidence intervals derived from the binomial uncertainty in $p_s$. Bernal Neira et al. [48] show that parameter settings strongly affect such metrics and vary between instances, so the cost of tuning parameters should be counted. That applies to the baseline as much as to the candidate.

For generative models, quality is usually a distributional distance such as FID [13]. The relevant energy metric is then the minimum energy at boundary $B$ needed to reach a quality threshold $Q^\star$:

where $\theta$ ranges over the system's operating points (steps, sweeps, temperatures, batch sizes). A fair advantage ratio is $A = \mathcal{E}_{Q^\star,\mathrm{base}}^{B} / \mathcal{E}_{Q^\star,\mathrm{cand}}^{B}$. It must use the same $Q^\star$, the same $B$ and the same evidence class on both sides, with both systems tuned under a declared, equal tuning budget [48].

3.5 Boundary decomposition and an Amdahl bound (scope: component substitution)

Decompose system energy at boundary $B$ as

Hold the workload fixed (same model, same algorithm, same number of updates). If a component accounts for a fraction $f$ of the baseline system energy and is improved by a factor $s$ while everything else stays the same, the system-level gain is

Eq. (10) is Amdahl's law [40] applied to energy. Its consequence is that a device-level ratio of $10^4$ produces a system-level gain of at most $1/(1-f)$ (Figure 1). Replacing the random-number source alone in a system whose energy is dominated by weighted sums, conversion and control cannot produce a large gain.

Scope limitation. Eq. (10) bounds component substitution only. Probabilistic architectures often also substitute the algorithm or model. They remove work instead of accelerating it, for example by replacing a large neural denoiser with a chain of small EBMs [15], or a sequential anneal with parallel trials [19]. In that case the baseline and candidate workloads differ, and the comparison must be written as

with all terms at the same $B$ and $Q^\star$. Eq. (10) applies to the hardware factor. The middle term, the candidate algorithm on baseline hardware, is exactly the same-model digital baseline that is missing from the reviewed generative-model claims (§5.1d). Our search found no controlled study that separates the two factors on a matched energy–quality ledger. The nearest datum is the DTCA paper's own same-hardware comparison: a monolithic EBM's energy consumption is "several orders of magnitude larger due to the glacially slow mixing" than the DTM's [15]. That is an algorithm-only factor, and it is modelled.

3.6 Thermodynamic floor

The Landauer bound [12] gives $k_BT\ln 2 \approx 2.87\times10^{-21}$ J per erased bit at 300 K. A modelled 2 fJ per p-bit update, the cell energy assumed in the DTCA model [15], is about $7\times10^{5}$ times this floor. Practical probabilistic hardware therefore operates far from thermodynamic limits, and its advantage, if any, comes from architectural avoidance of digital emulation overhead rather than from approaching fundamental physics. This bears on how "thermodynamic computing" is presented. The physics motivates the architecture; it does not by itself bound the achievable efficiency.

3.7 Denoising thermodynamic models

The DTCA work [15] addresses a known obstacle. EBMs are trained with gradient estimates drawn from MCMC samples, as in contrastive divergence [39], so slow mixing degrades both training and inference, and expressive monolithic EBMs have rugged landscapes that mix slowly. The proposed denoising thermodynamic model (DTM) chains $T$ simpler EBMs. Each EBM performs one conditional denoising step, analogous to diffusion models [14], so each step samples a better-conditioned distribution. Training adds an adaptive correlation penalty (ACP). ACP periodically measures each layer's autocorrelation at the sampling delay and adjusts a per-layer penalty weight to keep sampling tractable. The paper's energy model is

for an $L \times L$ grid with $K_{\mathrm{mix}}$ Gibbs iterations per denoising step. The paper reports $L = 70$ in most cases, $K_{\mathrm{mix}} = 250$ at inference, local connectivity of typically 12 neighbours, and a modelled $E_{\mathrm{cell}} \approx 2$ fJ. With these values Eq. (11) gives about 2.5 nJ per denoising step and about 20 nJ per image for $T = 8$. This is our arithmetic on the stated parameters, offered only as an order-of-magnitude illustration. The paper does not report this figure, and we have not reconciled it with the paper's plotted energies (§9). Eq. (11) contains no term for weight loading, sample transfer to a host, readout, memory or calibration. The authors state that communication with external hardware is excluded. The model is framed around inference: the Figure 1 axis of [15] is "the energy needed for generating a single new image using the trained model (inference)". Training energy, which relied on GPU simulation with $K \approx 1000$ Gibbs iterations per gradient estimate plus the ACP controller, is not part of the ~10,000× figure. "Thermodynamic computing" in this context therefore denotes an architecture whose physics motivates the design. It is not a measured thermodynamic efficiency (§3.6).

4. Review of physical probabilistic-computing demonstrations

4.1 Evidence map

Table 1 lists the demonstrations examined, ordered by integration level, and shows what was actually built and measured. Abstract-level ratios are handled separately in §5 and §7. The entropy-source column separates physically stochastic systems from systems that use pseudo-random number generators (PRNGs).

Table 1. Probabilistic-computing demonstrations reviewed (primary sources accessed 11 October 2026). Entropy: PHYS = physical noise source; PRNG = digital pseudo-random; HYB = physical source disciplining digital PRNGs.

4.2 What the evidence map shows

Physically real progress is substantial. Entropy sources are now demonstrated in standard or near-standard processes:

• CMOS shot noise [15] and 180-nm thermal noise [22];
• 130-nm sMTJ and V-MTJ integration [21, 36];
• CMOS-integrated VCMA MRAM [20];
• ferroelectric random-telegraph noise on 6-inch wafers [25];
• charge-trap FETs adapted from flash structures [26].

Calibration-stable operation across voltage and temperature corners has been measured [22]. A DAC-free 130-nm ASIC with 1,143 p-bits has been built and has factorised a 24-bit semiprime in its revised version [21]. The claim that a physical sampler can be built in a manufacturable process has moved from hypothesis to demonstration.

The best-documented integrated system is still board-dominated and entropy-limited. The Duffee et al. preprint is the most completely documented physically stochastic ASIC in the review [21]:

• Power: 395 mW for the ASIC and its control board, against 9 mW for the entropy-source board. Entropy is about 2% of measured board power (our arithmetic).
• Energy per bit: a device-level entropy cost of 34.4 pJ per bit in the experiment against a 0.43 pJ projection, a gap of about 80× (our arithmetic). The authors compute both figures from entropy-source power and read/write speed. The board-level cost is far higher: 9 mW at 0.307 kbit/s is about 29 µJ per bit (our arithmetic), assuming all TRNG-board power is attributed to bit generation at that rate. The experimental bit rate was limited by I/O.
• Randomness quality: the raw bitstream passed 2 of 11 NIST tests. The ASIC experiments used these raw bits; XOR post-processing, which requires additional devices and energy, was needed to pass all tests.
• Task quality: 67.5% valid end states on a 6-bit problem. No autocorrelation, ESS or same-task digital baseline is reported.

These are honest first-silicon numbers, and the paper is explicit about its projections. Measured and projected device-level figures currently differ by about two orders of magnitude, and board-level entropy costs are many orders of magnitude above device-level figures. One co-author is affiliated with a magnetic-storage company, so the paper is partly industry-authored.

The weighted sum is usually off-device. In every row except the all-digital systems (rows 3, 9, 13, 14) and the DAC-free ASIC (row 6), the weighted sum $I_i$ of Eq. (2) is computed by an FPGA, external op-amps or software.

The largest systems are digital. The million-p-bit machine [27], the 27,648-spin accelerator [28] and the 2022 sparse Ising machine [9] use PRNGs. Physically stochastic p-bits are not currently needed to reach scale.

The flagship generative-AI result has no array. The DTCA's measured hardware is one RNG circuit. Everything at array and system level is simulated and modelled [15].

5. Device-level versus system-level efficiency

5.1 Where the energy goes

Five recurring patterns separate device-level from system-level efficiency.

(a) Converters, interfaces and helper logic dominate measured prototypes. In the 144-MTJ processor [19], the MTJ-based simulated annealer "operates more slowly than its CPU counterpart" because of "peripheral circuit limitations", chiefly DAC/ADC throughput. The MTJs switch in nanoseconds, but the system runs on 4 µs pulses.

In the 180-nm CMOS p-bit study [22], the p-bit core consumes about 0.35 mW (6.95 pJ/bit × 50 MHz; our arithmetic), while a Vivado post-implementation report estimated 3.647 W for the FPGA board implementing weighted sums (2.954 W dynamic, 0.693 W static). On that reported basis, FPGA power is about 1.05 × 10⁴ times the derived power of one p-bit core, or about 1.3 × 10³ times that of eight cores; this is a tool estimate, not a measured wall-plug comparison. The authors caution that the FPGA figure "should not be interpreted as the optimized power of a custom integrated p-circuit" and state that the work "does not demonstrate full-system scalability".

In the 1,143-p-bit ASIC [21], the entropy-source board drew 9 mW against 395 mW for the ASIC and control board. The bit rate was limited by I/O, not by the devices. Across these three cases, measured system energy and throughput are set by the non-stochastic parts of the system.

(b) Headline efficiency is often computed inside a narrow boundary. The DTCA energy model (Eq. 11) counts RNG, bias, local wiring and clock, and wiring is about half the modelled budget. Communication with external hardware and training are excluded. The Z1T estimate [16] excludes the final dense logit readout, Z1↔FPGA data movement and the required chip count (§7.2). The Duffee figures are board-level, not wall-plug [21].

(c) Comparator energy is estimated asymmetrically, in both directions. We audit errors on both sides of each comparison.

• Assumptions that favour the candidate. In [16], the H100 runs the same next-token step densely, without exploiting sparsity, for a very small model at batch 1. GPUs are typically far from efficient in that regime. In [26], the CPU comparator is a software p-bit at about 4.7 mJ per operation, which is far above what optimised digital p-bits achieve [9, 27, 28].
• Assumptions that favour the baseline. In [15], GPU energy is FLOPs divided by the manufacturer's FLOP-per-joule specification, which the authors state "underestimates the actual values". Underestimating GPU energy lowers the reported advantage, so on this term the DTCA ratio is conservative.
• Assumptions of unknown direction. In [19], CPU power is utilisation multiplied by nominal power and GPU power is a flat 90 W, while the MTJ system is estimated from component power. None of these is a measured wall-plug figure, and the sign of the resulting error is not established. In [16], the H100 energy is derived from a peak per-FLOP figure scaled by an assumed utilisation. Whether this over- or under-states measured H100 energy for this workload is not established.
• PRNG-side baselines. Device papers often compare a physical entropy source with software PRNGs. One study compares SPICE-simulated sMTJ sampling energy with measured PRNG energy from Antunes and Hill [50] and reports a factor of 5,649 over PCG32 for Float16 sampling, while calling the comparison "somewhat limited" [51]. That is a mixed-class comparison (§8, element E1). Antunes and Hill measured PRNG energy across C, Python, NumPy, TensorFlow and PyTorch and found that machine-learning-library implementations used about 10% more energy than the C versions [50]. This shows that baseline implementation choices alone move the PRNG side by measurable amounts.

(d) Model-class substitution. The DTCA baselines are a VAE, a GAN and DDPMs on a GPU [15]. The result compares a different model on a different machine, not the same EBM sampled by Gibbs on a GPU. Both comparisons are legitimate, but they answer different questions; Eq. (10a) separates them. The same-model digital baseline (the middle term of Eq. 10a) is missing.

(e) Peripheral reduction is a real research direction. DAC-free p-bits [21], cointegrated analog weighted sums [26], CMOS-integrated MRAM [20] and multichip digital designs that report I/O-inclusive energy [28] all address pattern (a). The peripheral share is an engineering variable, not a law of nature. None of these works yet reports a closed-boundary, quality-matched comparison against a tuned digital baseline.

5.2 Applying the boundary bound

Eq. (10) is valid only for component substitution with a fixed workload (§3.5).

• Single-p-bit CMOS demonstration [22]. The p-bit core is about $10^{-4}$ of measured board power. Any improvement of the entropy source leaves system energy essentially unchanged ($G \le 1.0001$) until the weighted-sum and control path is integrated.
• 1,143-p-bit ASIC [21]. The entropy-source board is about 2% of measured board power (9 mW of about 404 mW in total). Even a perfect entropy source would reduce the measured setup's power by at most about 2%. The device-level 34.4 → 0.43 pJ/bit improvement and the board-level entropy cost are different quantities, and neither changes this bound. This is a component-substitution statement about the measured setup, not about future integrated designs.
• Z1T vendor estimate [16]. Z1 sampling is 8.74 nJ of 294.52 nJ per token (about 3%) with the readout excluded, and about 0.006% of the 136.4 µJ readout-included figure. Within the vendor's model, any further improvement of the sampler changes per-token energy by at most about 3%.
• Hypothetical integrated sampler. If co-design moved 90% of baseline energy into a stochastic fabric $10^4$ times more efficient, the gain would be about 10. Large ratios require $f \to 1$ or an algorithmic factor in Eq. (10a), meaning the probabilistic design must remove or absorb the non-sampling work.

5.3 Table of boundary audits

Table 2. Boundary audit of principal efficiency claims.

Table 2a. Z1T per-token energy: a conditional, modelled sensitivity interval (all inputs vendor-modelled [16]; ratios are our arithmetic). Values > 1 favour Z1T. None of these values is a measurement.

The defensible statement from Table 2a is conditional: within the vendor's own model, the sign of the advantage depends on where the dense readout runs and on GPU utilisation. Measured Z1 silicon, a measured H100 at a stated batch size, and a stated readout placement would all be needed to replace the interval with a number.

6. Sampling quality, autocorrelation and effective sample size

6.1 What is reported

The reviewed hardware literature reports sampling quality in five ways, none of which is an effective sample size of the chain:

1. Randomness-test pass rates (NIST SP 800-22) on raw or whitened bitstreams [21, 22, 25]. These certify the entropy source, not the Markov chain. In the 1,143-p-bit ASIC, the raw V-MTJ bitstream passed 2 of 11 tests and the ASIC experiments used raw bits; XOR post-processing of four streams was needed to pass all 11 [21]. Source quality is therefore a live engineering issue. A perfectly random source driving a poorly mixing chain would still produce correlated samples.
2. Source-level autocorrelation, such as the DTCA RNG's τ₀ ≈ 100 ns [15] or two-state transition probabilities for FTJ random-telegraph noise [25]. These describe the source, not the chain.
3. Distributional distance at convergence, such as KL divergence to the Boltzmann distribution for a 5-p-bit adder [23] or FID for generated images [15, 25]. These are bias checks in the sense of Eq. (4a), and they are valuable.
4. Optimisation outcomes: TTS95 [19], success probability [20, 26], fraction of valid end states (67.5% for the factorisation of 35 [21]), tour length [24], residual energy [27]. For the factorisation of 1539 in [22], the correct factor pair accounts for 840 of 100,000 samples (0.84%).
5. Acknowledgement without measurement. The 250-MTJ paper states that "MCMC samples are autocorrelated" and that "this correlation is fundamental to ensure the system samples from the chosen energy landscape" [18], but reports no mixing time, autocorrelation curve or ESS.

The DTCA paper comes closest. It estimates mixing time by fitting an exponential to large-lag autocorrelation, and its ACP uses measured layer autocorrelation during training [15]. These are chain-level quantities, but they come from simulation, and the energy result is denominated in modelled raw samples at fixed $K_{\mathrm{mix}}$.

Not found in the reviewed literature (bounded absence): any fabricated probabilistic-hardware study reporting the chain's integrated autocorrelation time, ESS, ESS per second, or energy per effective independent sample on a workload. Table 0 lists the searches behind this statement. The closest measured primitives are source-level autocorrelation functions and randomness tests. The correlation-time analysis of Böhm et al. [31], sometimes cited as a measured sampling rate, is based on numerical simulations. The statement is limited to what we could search without bibliographic databases (§2.5).

6.2 Why the missing quantity matters

The ratio between raw and effective throughput depends on the problem and can be large. Three mechanisms appear in the reviewed sources, and a fourth arises from the statistical conditions in §3.2.

• Chain correlation. Berns et al. [29] find longer autocorrelation for stochastic Ising-machine sampling than for the baseline. Any FPS advantage must be discounted by this ratio (Eq. 5).
• Parallel-update error (bias, not only variance). Synchronous updates of coupled spins violate the Gibbs conditional. This changes the distribution being sampled, $\tilde p$ in Eq. (4a), and is not just a matter of correlation. Onizawa and Hanyu [30] describe oscillations under excessive simultaneity. The million-p-bit system [27] finds that infrequent inter-FPGA exchange ($\eta = f_{\mathrm{comm}}/f_{\text{p-bit}}$ below a threshold) slows the decay of residual energy, a throughput–accuracy trade-off measured on real digital hardware.
• Source correlation, bias and drift. 1/f noise produces autocorrelation between successive output bits in CMOS p-bits [22], mitigated there by correlated double sampling. V-MTJ bitstreams showed bias attributed to residual stray field and thermal drift [21]. Lifetime behaviour is untested in the reviewed sources.
• Estimator optimism under positive correlation. Common lag-window (spectral) and batch-means variance estimators show significant negative bias for positively correlated series [44], so naively computed ESS would overstate the effective throughput of a strongly correlated physical sampler. Hardware ESS figures, once reported, should state the estimator and include a sensitivity check (C2–C3 in §3.2).

6.3 Does the randomness source matter?

Physical randomness is often motivated by the inadequacy of cheap PRNGs. The one matched trial we found tests this directly. In Singh et al. [23], the KL divergence of an LFSR-only solver saturates beyond about 10⁴ sweeps. Solvers whose LFSRs are clocked by sMTJs keep improving, and so does a solver using the Xoshiro PRNG. The physical source therefore fixed a low-quality PRNG and reached parity with a good one; it did not outperform the good one.

Two further observations point the same way. The X0 hardware experiment yields estimates "consistent with a software pseudorandom baseline" [17]. The largest systems reach scale with digital randomness [9, 27, 28]. The DTCA sampler is a Gibbs update driven by random bits with a controllable bias, and its measured RNG supplies exactly that bias response [15]. Nothing in the update rule requires the bits to come from a physical source.

Reading supported by the evidence: physical entropy can save energy and area at the source. Those savings are projected rather than measured at system level, and a mixed-class comparison is not evidence of them [51]. Physical entropy also repairs low-quality PRNGs. It has not been shown to improve task outcomes relative to a good PRNG at matched entropy rate. A trial demonstrating a unique task-level benefit of physical entropy was not found in the reviewed literature.

7. Detailed case studies and contradictory findings

7.1 Case study A: the denoising thermodynamic computer architecture

Publication history. The paper was posted as arXiv:2510.23972 (v1 28 October 2025; v2 10 December 2025) and published in npj Unconventional Computing 3, 30 on 2 July 2026 [15].

Claim. "...could achieve performance parity with GPUs on a simple image benchmark using ~10,000 times less energy" [15].

What is measured. An all-transistor RNG test chip shows a sigmoidal bias response and exponential autocorrelation decay with τ₀ ≈ 100 ns. A PDK Monte Carlo analysis with about 200 realisations per process corner assesses robustness. The chip is an instance of a previously published design and does not implement the architecture. No full DTCA device exists.

What is simulated and modelled. DTM training and sampling run in a JAX simulator ("thrml") on binarised Fashion-MNIST, plus a CIFAR-10 hybrid with an autoencoder embedding. Energy comes from Eq. (11) with $E_{\mathrm{cell}} \approx 2$ fJ, for inference only. GPU energy is FLOPs divided by the specification FLOP/J, which the authors state underestimates real GPU energy. That makes their ratio conservative on this term (§5.1c).

Strengths. The mixing–expressivity argument is physically sound. The paper identifies a real mechanism, offers modelling (denoising chains) and training (ACP) fixes, and measures its simulated chains' autocorrelation. It also states limits that matter for any scaling extrapolation:

• that scaling latent variables "only improves performance if the connectivity of the graph is also scaled; otherwise, performance can decrease";
• that "it would be naive to expect that a hardware-efficient EBM topology can be scaled in isolation";
• that the authors "don't yet know how to build progressively larger probabilistic AI systems";
• that the most effective proof would be "to demonstrate it on a real chip".

Limitations relevant to RQ1–RQ3.

• (i) Evidence class: SIM + MOD for every system-level number.
• (ii) Boundary: B0–B2; external communication and training excluded.
• (iii) Denominator: modelled raw samples at fixed $K_{\mathrm{mix}}$, not effective samples.
• (iv) Baseline: a different model class (the middle term of Eq. 10a is absent).
• (v) Scale: Fashion-MNIST, described by the authors as "very far from the state-of-the-art in terms of raw modeling power".
• (vi) Authorship: primarily authored by the company developing the hardware, with one academic co-author. The competing-interests statement was not visible in the retrieved text.
• (vii) Independent scrutiny: our targeted and adversarial searches found no independent peer-reviewed critique or replication (Table 0).

Verdict. This is an important architectural and theoretical contribution whose headline ratio is an inference-only modelled projection with one measured component. It should be cited that way. It is not evidence that probabilistic hardware has delivered a measured advantage. Nor is it a demonstrated thermodynamic efficiency (§3.6).

7.2 Case study B: Z1T sparse transformer-like models (vendor, 2026)

Claim. Z1T on a Z1 + FPGA system is about 139 times more energy-efficient per token than an H100 at 10% MFU [16].

Arithmetic as published. Z1 sampling 8.74 nJ + FPGA 285.78 nJ = 294.52 nJ per token. H100: 40.9 µJ (10% MFU), 8.17 µJ (50%), 4.09 µJ (100%), from 0.177 pJ/FLOP peak scaled by MFU, for the same next-token step run densely (11.55 M body parameters).

Exclusions stated by the vendor. The final dense logit readout; data movement between Z1 and FPGA; and "the required chip count is not modeled". The Z1 energy is projected "based on theoretical chip energy consumption of Z1 based on our best estimates", "anchored to reality from our experiments with similar pbits in X0".

Conditional sensitivity, not a verdict. With the vendor's readout-included estimate of 136.4 µJ per token, the modelled comparison ranges from about 3.3× worse (H100 at 10% MFU) to about 33× worse (100% MFU) (Table 2a). Every input to this interval is modelled. The H100 side is a per-FLOP model. The readout could run on a GPU or other accelerator, which the vendor says it may explore. The vendor's H100 baseline is a batch-1 estimate. Batching, or a measured H100 run, would change the H100 figures. We therefore report only the conditional interval and its dependence on assumptions, not a single ratio.

Additional deflators. The sparse model needs "about an order of magnitude more FLOPs" in training to match GPT-2-small loss [16].

Verdict. VEN + MOD. The work is a valuable, openly documented energy model with explicit exclusions. It does not establish a measured system advantage or disadvantage.

7.3 Case study C: board-level MTJ Ising machines (2026)

The two NUS-led Nature Communications papers [18, 19] report both device-level and system-level results and are candid about the gap between them.

• 144-MTJ processor [19]. The like-for-like sequential comparison (MTJ-SA against CPU-SA) is a loss for the MTJ system because of peripheral throughput. The measured advantages come from a parallel-trial algorithm on the MTJ fabric: 123× over MTJ-SA; 3.2× faster with 58.3% energy saving against a C++ CPU implementation; up to 8.9× over an H100. In the terms of Eq. (10a), most of the gain is an algorithmic factor that could in principle be realised digitally. The D-Wave comparison is a feasibility result on very small QAPs. Problem sizes are 9–144 spins.
• 250-MTJ PIM [18]. Exact 24-bit factorisation and Max-Cut on 200-node Biq Mac instances at 12.5 kHz. The 10¹⁵ FPS / 10⁻¹³ J figures are projections for a 1-Mbit ASIC. MCMC autocorrelation is acknowledged but not quantified.

These results support the hypothesis that the measured advantage is predominantly algorithmic. We have shown this for one system only [19] and do not generalise it. The competing hypothesis, that device integration [20, 21, 26] will remove the converter bottleneck, remains open.

7.4 Case study D: cointegration and the weighted-sum bottleneck

Park et al. [26] cointegrate charge-trap FET p-bits with an analog synapse array on an 8-inch wafer, so the weighted sum is computed in the array. This addresses pattern (a) in §5.1 directly. Two qualifications apply. Hardware results are limited to a 4-node Max-Cut: the 20-node and up-to-3,000-node results are simulations driven by measured device statistics. Current-to-voltage conversion was done by off-chip op-amps. The CPU comparison (about 4.7 mJ and 188 µs per software p-bit operation) is far above optimised digital p-bits [9, 27, 28] and is not a fair digital baseline. The work is a credible step toward closing the boundary, not yet a closed-boundary result.

7.5 Case study E: a 1,143-p-bit ASIC with a V-MTJ entropy source

Duffee et al. [21] is the most completely documented physically stochastic integrated system in the review. We read the preprint in full, together with the Version-of-Record abstract and Extended Data captions.

Measured.

• 130-nm SkyWater ASIC with 1,143 p-bits; random bits drawn from a separate V-MTJ TRNG board, with no DACs.
• Power: 395 mW for the ASIC and control board while solving; 9 mW for the TRNG board.
• Entropy cost: device-level 34.4 pJ per bit at 0.307 kbit/s in the experiment. The rate was limited by ASIC control-board I/O and a conservative 3.26 ms write/read procedure. The device lifetime was observed at about 10⁷ bits. At board level, the 9 mW TRNG board corresponds to about 29 µJ per bit at that rate (our arithmetic).
• Randomness: raw bitstream passed 2/11 NIST tests; XOR4 passed 11/11. The ASIC experiments used the raw bits.
• Task: 6-bit factorisation of 35 with 67.5% valid end states after 8,192 iterations. The Version of Record adds a revised second ASIC that factorised the 24-bit semiprime 12,441,691, with the correct pair appearing in a plurality of trials.

Modelled. 0.43 pJ per bit from a single write pulse; 45-nm and 7-nm scaling designs from predictive PDKs; a 20-bit factorisation run in simulation; projections toward millions of p-bits.

Not reported. Autocorrelation, ESS, a CPU/GPU baseline on the same task, wall-plug energy, and energy per solution. The paper states that its scaling projections do not evaluate the time to reach a solution.

Assessment. The study demonstrates integration at a meaningful scale and is transparent about the gap between experiment and projection. It does not provide a quality-matched comparison, and its measured power is dominated by the non-stochastic board (Eq. 10). Its Supplementary Information and Version-of-Record main text were not accessible to us (§2.6). Some statements may therefore be refined in the published version.

7.6 Contradictions and disputes

Table 3. Contradictions and qualifications identified in the published literature and its secondary reporting.

8. A reporting checklist for probabilistic-hardware claims

8.1 Position relative to prior methodology

This section presents a practical reporting checklist, labelled "QBSE" (quality-matched, boundary-closed sampling evaluation) for cross-reference only. It is a synthesis of established methods. We do not claim it as an invention, as validated, or as a community standard. Table 5 attributes each element to prior work, and Table 4 applies only objective reported / not reported checks.

ESS per second is already a routine efficiency measure in statistical software benchmarking. Energy per effective sample (Eq. 6) is its direct energy analogue, not a new concept.

Table 5. Prior-art mapping: every checklist element has an established source.

Remaining claim of distinctness. We did not find, in the literature we could search, a guideline that requires E3 (chain diagnostics on hardware traces), E2 (closed boundary with $f$ reported) and E5 (same-model tuned baseline) together for probabilistic-hardware efficiency claims. The narrow, conjunctive reporting requirement is the only contribution we claim. It is bounded by our search and has been examined only in AI-assisted critical passes. An independent methods critique would strengthen or overturn it.

8.2 Checklist elements

• E1. Evidence class. Every number carries a class (M-sys, M-dev, SIM, MOD, VEN, SEC). A ratio with different classes on its two sides is flagged mixed-class and is not used as a headline [51].
• E2. Boundary ledger. Every energy number carries a boundary B0–B5 (Figure 2) and an inclusion/exclusion ledger over Eq. (9), including the fabric's energy fraction $f$. Headline comparisons with CPUs or GPUs are made at B4, or at B3 with each excluded term quantified. Bounds from Eq. (10) are labelled as component-substitution bounds.
• E3. Chain diagnostics. Report autocorrelation functions for at least one bulk and one tail statistic; $\tau_{\mathrm{int}}$ with its estimator and truncation rule; bulk and tail ESS; split-$\hat{R}$ over at least four independent chains, with targets such as $\hat R < 1.01$ and ESS ≥ 400 [5]; warm-up length and how it is charged (Eq. 6); a sensitivity check across variance estimators [44, 52]; and at least one bias check against an exact or high-accuracy reference (Eq. 4a) [23, 46]. NIST-type tests are reported in addition, never instead.
• E4. Efficiency metrics. Report $\mathcal{E}_{\mathrm{eff}}^{B}$ (Eq. 6) for the slowest-mixing statistic; ETS($p$) at $p \ge 0.99$ with binomial confidence intervals [47]; or $\mathcal{E}_{Q^\star}^{B}$ (Eq. 8) at pre-registered quality thresholds.
• E5. Baselines. (a) The same model on a tuned digital sampler. (b) The best available model on conventional hardware at equal quality. (c) A digital emulation of the same architecture with a good PRNG. Baseline power is measured at the same boundary, never derived from TDP, flat assumptions or per-FLOP peaks. Batch size and utilisation are tuned for energy, and the tuning budget is declared and equal on both sides [48]. When algorithms differ, the algorithmic and hardware factors of Eq. (10a) are reported separately.
• E6. Scale. At least one instance class that takes the tuned baseline non-trivial time, from public libraries.
• E7. Lifecycle. Calibration procedure, energy, time and frequency under drift; chip-to-chip spread (for example, up to 14.08 percentage points of output-probability difference in [22]); device endurance (for example, about 10⁷ bits observed for one V-MTJ [21]).
• E8. Provenance. Raw traces, code, seeds, PDK corners and author affiliations released or declared; vendor-authored results labelled until independently replicated.

8.3 Objective reporting audit of the principal studies

Table 4 records whether each item is reported in the text we read. The entries are binary, checkable facts, not quality scores. ✓ = reported; ✗ = not reported in the text read; ◐ = partly reported (the reason is given in the accompanying audit); n/a = not applicable.

Table 4. Reporting audit (objective items only; based on the text actually read, §2.6).

No study reports ESS or $\hat{R}$, and none reports a measured same-model digital baseline. This is consistent with the field's stage of development and is not a criticism of individual papers. Several studies are notably transparent about their own boundaries [15, 16, 21, 22].

8.4 Statement rule for advantage claims

An advantage should be stated as

with a 95% interval from instance-level and chain-level resampling. The boundary $B$, quality threshold $Q^\star$, evidence class, baseline type and tuning budget are stated in the same sentence as the number. A projection is reported as $\hat{A}$, labelled MOD, with its excluded terms listed. Where the inputs are themselves modelled, a conditional interval in the style of Table 2a is preferred to a point estimate.

9. Limitations, uncertainty and unverified claims

1. No systematic database search. Scopus, Web of Science, IEEE Xplore and the ACM Digital Library were not used. Absence statements rest on the searches in Table 0 and are bounded accordingly. This is the main methodological limitation of the review.
2. Unread full texts and supplements (§2.6): the Duffee et al. Version of Record and Supplementary Information [21]; the Li et al. full text [20]; the supplements of [18, 19, 22, 25]; the full bodies of [34, 45, 48, 49]. Entries in Tables 1, 2 and 4 for these sources may change if those texts are read.
3. No independent statistical review. Conditions C1–C5, Eqs. (4)–(6), (4a) and checklist item E3 are drafted from the cited statistical literature. Their wording and application to hardware have been checked only in AI-assisted editorial passes, not by an independent statistician. Eq. (4a) is an asymptotic decomposition. Eq. (6) assumes independent, equally mixing chains.
4. Fast-moving field. Several key sources are 2026 preprints [27–30, 36] and may change on revision. Two sources already differ between their preprint and published versions ([20], [21]; Table 3, C8–C9).
5. Derived numbers. The following are our arithmetic on published figures and are only as reliable as those figures:
   • the Eq. (11) illustration (~20 nJ per image), not reconciled with the plotted values in [15];
   • Table 2a;
   • the FPGA-to-core ratio [22];
   • the entropy-board share, the board-level ~29 µJ-per-bit estimate and the ~80× device-level gap [21].
6. Reporting audit. Table 4 records what we found in the text we read. An item marked ✗ may be reported in an unread supplement.
7. No cross-technology ranking. The review compares claims with their own baselines and boundaries. It does not rank stochastic, digital, analog or photonic substrates against one another, because the reviewed results use incomparable tasks, quality metrics and boundaries.
8. Interpretive risk. We have tried to scrutinise baselines as closely as candidates (§5.1c) and to give positive evidence full weight (§4.2, §5.1e, §7.1, §7.4, §7.5). The critical passes used in preparing this version were AI-assisted, so readers should judge independently whether the balance was achieved.

Excluded from evidence:

• a heat-emission ratio above 10¹¹ attributed in secondary notes to [33], which we did not find in the text we could retrieve;
• an attribution of ESS and burn-in accounting to a rare-event estimation preprint (arXiv:2608.26840), whose abstract contains neither;
• vendor figures for an optoelectronic p-bit system, available to us at abstract level only;
• roadmap values for per-bit energy that we could not re-verify;
• numbers for a hybrid ReRAM–sMTJ Ising machine reported only in news coverage;
• any independent measurement of Z1 silicon, of which none was found.

10. Future scientific research questions and conceptual validation protocols

The following protocols are conceptual designs. None has been carried out, funded or scheduled by the authors' organisation, and none implies access to hardware.

Q1. What is the energy per effective sample of a physical p-bit array on a standard workload? VP-1 (re-analysis, no new hardware). Request raw spin trajectories from the authors of published systems [18, 19, 22, 27], or use them where they are already public. Compute $\tau_{\mathrm{int}}$, bulk/tail ESS and $\hat{R}$ with at least two variance estimators [5, 44, 52]. Run one bias check per Eq. (4a). Combine with reported system power to obtain $\mathcal{E}_{\mathrm{eff}}$ at the stated boundary. Falsifiable expectation: on frustrated instances, $\tau_{\mathrm{int}}^{(\mathrm{sweep})} \gg 1$, so per-flip efficiency overstates per-effective-sample efficiency by more than an order of magnitude. If $\tau_{\mathrm{int}} \approx 1$ on realistic instances, the concern is substantially weakened.

Q2. How large are the algorithmic and hardware factors of the DTCA ratio (Eq. 10a)? VP-2 (simulation). Run the same trained DTM with tuned chromatic Gibbs on a GPU, with energy measured at B4 at the batch size that minimises energy. Compare against (a) the paper's modelled hardware energy and (b) a tuned small diffusion model at matched FID. Report training energy separately.

Q3. How large is $f$ for integrated designs? VP-3 (boundary audit). Construct Eq. (9) ledgers for fabricated systems with power data, prioritising designs with integrated weighted sums [20, 21, 26]. For [21], this requires the Version of Record and its supplement.

Q4. Does physical entropy improve task outcomes over a good PRNG at equal entropy rate and energy? VP-4 (ablation; would require third-party hardware access). Extend the matched trial of [23]: on one architecture, use (i) a low-cost LFSR, (ii) a good PRNG at equal bit rate and (iii) the physical source with and without XOR post-processing [21]. Measure KL divergence or task quality versus sweeps, and source energy at B1 and B3. Falsifiable expectation: parity with the good PRNG [23]; energy differences confined to the source.

Q5. What does calibration cost over a lifetime? VP-5 (longitudinal). Track output-probability drift and device endurance, the recalibration frequency needed to keep $\hat{R}$ and quality in bounds, and the energy charged to $\mathcal{E}_{\mathrm{eff}}$.

Q6. Can parallel-update bias be traded for throughput predictably? Building on the η-threshold result [27] and update-dynamics analysis [30], measure ESS per joule and bias (Eq. 4a) as functions of update concurrency on physically stochastic fabrics.

Q7. Are there workloads where GPUs are structurally weak enough for $f \to 1$ or a large algorithmic factor? Candidates include sparse, locally connected EBMs [15], neural-quantum-state sampling [29] and rare-event estimation. Each needs a pre-registered quality threshold and a same-model digital baseline.

11. Discussion

11.1 Answers to the research questions

RQ1. Measured results exist at device and cell level (entropy sources, switching curves, randomness tests, energy per random bit) and at small-system level: 144–1,143 physical p-bits, small optimisation instances (for example 9–144-spin QAPs, 200-node Max-Cut and a 96-city TSP), and factorisation up to 24 bits. Every reviewed energy advantage of three or more orders of magnitude over GPUs is modelled, simulated, projected or vendor-claimed, or rests on a system boundary we could not verify [20]. The only physically stochastic integrated system with published board power [21] reports no task-level comparison with digital hardware.

RQ2. Headline figures are typically stated at B0–B2. Where closing the boundary was computable from published data, measured systems are dominated by non-stochastic electronics: FPGA helper about 10³–10⁴ × the p-bit core [22]; entropy board about 2% of measured board power [21]. For the vendor-modelled Z1T case, closing the boundary turns a single ratio into a conditional interval that spans both signs (Table 2a).

RQ3. No reviewed fabricated sampler reports ESS or energy per effective sample. This absence is bounded by our search. The resulting uncertainty is at least a factor of $\tau_{\mathrm{int}}$ (Eq. 6), which is unknown for every reviewed hardware system. A sampler bias term (Eq. 4a) is also unquantified for most of them. Any future ESS figure must state its estimator and the conditions C1–C5 under which it is valid.

RQ4. The strongest positive evidence is that physical samplers are now manufacturable, operate across corners, integrate at the scale of about a thousand p-bits [21], and in some designs integrate weighted sums [20, 26]. Algorithmic restructuring (DTMs, ACP, parallel trials, tempering) relieves mixing limits [15, 19, 42]. A real advantage requires three things together:

• the probabilistic design must absorb or remove most of the system's work ($f \to 1$, or a large algorithmic factor in Eq. 10a);
• its chains must mix with small bias on target workloads;
• tuned, same-model digital baselines must be structurally inefficient on those workloads.

Whether all three hold at once on a useful task remains an open empirical question.

RQ5. All checklist elements already exist in established methodology (Table 5). The defensible contribution is a narrow, conjunctive reporting requirement, offered for independent critique.

11.2 Interpretation

Two simplifications should be avoided. The first is that probabilistic hardware is already 10⁴ times more efficient than GPUs. No reviewed measurement supports this. The second is that probabilistic hardware is an illusion because system overhead swamps device gains. The overhead observed is largely that of first-generation test infrastructure (FPGAs, discrete converters, control boards, I/O-limited procedures), and several 2025–2026 works reduce it directly. The current evidence does not decide between these positions. The finding is useful because it identifies which measurements would decide the question: $f$, $\tau_{\mathrm{int}}$ with bias checks, and measured, tuned, same-model baselines.

The field's leading papers are often more careful than the way they are discussed. The DTCA authors call their work a first step and say a real chip is needed. The CMOS p-bit authors disclaim system scalability. The ASIC authors separate experiment from projection in one table. The Z1T vendor lists its exclusions. The reporting gap arises when abstract-level ratios circulate without their qualifiers.

12. Conclusion

Physical probabilistic computing has made real progress in devices and small integrated systems, including a 1,143-p-bit ASIC with a magnetic entropy source. Its most widely cited efficiency advantages, however, remain projections from simulators, energy models and vendor estimates. They are typically stated at narrow system boundaries and in raw rather than effective samples. In the measured systems we could examine, non-stochastic electronics dominate power. The measured device-level entropy cost is about two orders of magnitude above its projection, and the board-level cost is higher still. Where a vendor's own model can be extended to close the boundary, the sign of the advantage depends on assumptions that have not been measured. Whether physical samplers can deliver a quality-matched advantage at a closed boundary therefore remains unresolved in the literature we could review.

Four quantities would resolve it:

• the share of system work the stochastic design absorbs or removes;
• chain-level effective sample size on realistic workloads, under stated statistical conditions;
• sampler bias;
• the measured energy of a tuned, same-model digital baseline at the same boundary and quality.

The reporting checklist we describe asks for these together. Its components are established methods, and it is offered for independent scrutiny rather than as a new methodology.

Declarations

Publication status. Ethen Research Lab · Research Review · Version 1.0 · Not Peer Reviewed. This is a literature-based review self-published by Ethen Research Lab; it reports no original hardware experiments. It has not been submitted to or accepted by any journal and has not undergone independent human peer review.

Author contributions. Shadab Chow is the named author of this literature-based review. AI-assisted research, drafting and editorial work are disclosed below. Responsibility for final content and release rests with the named author.

Data and materials availability. No new data were generated. All quantitative values come from the cited third-party sources. Derived values (marked "our arithmetic") can be reproduced from the stated equations and cited inputs. They are itemised in the claim and reference audit maintained with this version, which is available from the corresponding author on request.

Code availability. A supplementary Python checker for the Figure 1 formula and selected vendor-model arithmetic in Table 2a is published with this article: reproducibility-check.py. The original figure plotting source was not supplied and is not claimed to be available. No original experimental code or datasets are reported.

Competing interests. The author reports none. The author is affiliated with Ethen Research Lab / Upcube, which conducts literature research and conceptual design work on advanced computing, including probabilistic hardware concepts. It has fabricated no hardware, holds no measured results on the systems discussed, and makes no novelty or patentability claims in this work. No freedom-to-operate opinion is expressed or implied.

Funding. Not applicable (author-declared; no dedicated funding reported for this review).

Use of AI tools. An AI system (Claude, Anthropic) assisted with this review. Its roles were:

• retrieving and checking sources;
• recomputing derived numbers;
• drafting and revising text;
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References

Accessed 11 October 2026. Depth of verification: [FT] primary full text read (at least the sections cited); [P] primary abstract, landing page or figure captions read; [M] bibliographic metadata verified against Crossref or the arXiv record; [K] cited from standard bibliographic knowledge, not re-retrieved for this version. Preprints are marked as such.

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